| US 7,330,052 B2 | ||
| Area efficient fractureable logic elements | ||
| Sinan Kaptanoglu, Belmont, Calif. (US); Bruce B. Pedersen, Sunnyvale, Calif. (US); James G. Schleicher, Los Gatos, Calif. (US); Jinyong Yuan, Cupertino, Calif. (US); Michael D. Hutton, Mountain View, Calif. (US); and David Lewis, Toronto (Canada) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Sep. 22, 2005, as Appl. No. 11/234,538. | ||
| Prior Publication US 2007/0063732 A1, Mar. 22, 2007 | ||
| Int. Cl. G06F 7/38 (2006.01); H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—40 [326/41; 326/47] | 23 Claims |
| 1. A fracturable logic element comprising:
a first, second, third, and fourth two-input lookup tables (2-LUTs), wherein each 2-LUT includes four memory elements, each
memory element configured to hold one data bit;
a set of six inputs; and
a control circuit configured to operate in a first mode and a second mode,
wherein, when the control circuit operates in the first mode, a first combinatorial output is generated using four of the
set of six inputs and the first, second, third, and fourth 2-LUTs,
wherein, when the control circuit operates in the second mode, a second combinatorial output is generated using a first subset
of three of the set of six inputs and the first and second 2-LUTS, and
wherein, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset
of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets
of the set of six inputs.
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